This invention relates in general to integrated circuit devices having a multilevel configuration and, more particularly, to an improvement in such devices which greatly simplifies the design and fabrication thereof.
Multilevel integrated circuits are normally arranged to have one or more layers of conductive material which are formed into conductor and/or gate electrodes and an additional layer of metal for interconnect purposes. In such circuits, the layer of interconnect metal is distinct from the lower layers of conductive material and is separated from each of these lower layers of conductive material by a layer of insulating material. Accordingly, these prior art devices are typically arranged to have a separate conductor layer for each lower level of conductors and/or gate electrodes and an additional conductor layer for interconnect purposes.
It is an object of the present invention to provide a multilevel device wherein a single "conductor/interconnect layer" is used for interconnections and for gate electrodes and other conductors.
A further object of the present invention is to provide a multilevel device wherein a thick interlayer insulator is selectively located between the metal of the conductor/interconnect layer and the underlying substrate and lower level conductor layers to thereby isolate this layer of metal from the substrate and lower level conductor layers.
It is an additional object of the present invention to provide a method for fabricating a multilevel device of the character described herein.
Other objects of the invention, together with the features and novelty of the invention, will appear in the course of the following description.